FPGA Prototyping by VHDL Examples by Pong P. Chu

Author:Pong P. Chu
Language: eng
Format: epub
Publisher: Wiley
Published: 2011-08-04T16:00:00+00:00

The main part of the code is the FSM, which screens for the break code and coordinates the operation of two other modules. It checks the received packets in the wait_brk state continuously. When the F0 packet is detected, it moves to the get.icode state and waits for the next packet, which is the make code of the key. The FSM then asserts the code.done.rtt ck signal for one clock cycle and returns to the wait_brk state.

Figure 8.5 Block diagram of a keyboard verification circuit.

8.4.2 Verification circuit

We design a simple serial interface and decoding circuit to verify operation of the PS2 keyboard interface. The top-level block diagram is shown in Figure 8.5. The circuit converts a key's make code to the corresponding ASCII code and then sends the ASCII code to the DART.The corresponding character or digits can be displayed in the HyperTerminal window. The HDL code for the conversion circuit is shown in Listing 8.4.

Listing 8.4 Keyboard make code to ASCII code

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